Serial interfaces are widely used for data communications between a control unit and its peripherals. In particular, SPIs are commonly associated with microprocessors and their peripherals. A block diagram of a typical prior art SPI interface is shown in FIG. 1. A control circuit PIN CONTROL LOGIC has a pin SCK for either receiving or outputting a clock signal, depending on whether the SPI is in a slave or in a master device, respectively. It also includes a pair of input/output pins MISO (master in/slave out) and MOSI (master out/slave in), as well as another pin SS (Slave select) for allowing external configuration of the SPI interface as a slave device, or for selecting an external peripheral.
If the interface is in a master device, the pin MISO serves as an input for signals coming from the slave device, and the pins MOSI and SS serve as output pins providing signals for the slave device. The opposite happens when the SPI interface is in a slave device.
A pair of FIFO memory buffers TRANSMIT BUFFER and RECEIVE BUFFER respectively store data to be transmitted and received data. These buffers are connected to a bus DATA IN for data to be transmitted to the peripherals, an addresses bus ADDR for memory locations where data in transit is to be stored, and a bus DATA OUT for data received from the connected peripherals. Shift registers RECEIVE SHIFT REGISTER and TRANSMIT SHIFT REGISTER serially receive and transfer, respectively to the circuit PIN CONTROL CIRCUIT received data or data to be transmitted.
The buffers are connected to circuit blocks (i.e., counters) POINTER and CURRENT POINTER which generate a pointer to the memory location to be read. More particularly, the counter POINTER increments the current value of the pointer stored in the register CURRENT POINTER. The comparator COMP compares the current value of the pointer with a predetermined maximum value, generated by the block END POINTER, and eventually indicates that all bits of the word have been read when the maximum value is reached.
The control register CTRL exchanges information for configuring the SPI interface with the control circuit PIN CONTROL LOGIC. It may also load a certain default value in the circuit CURRENT POINTER. Another kind of SPI interface is the so-called “queued SPI” (QSPI), disclosed in U.S. Pat. Nos. 4,816,996 and 4,958,277 to S. C. Hill et al., which is schematically illustrated in FIG. 2. It differs from the interface of FIG. 1 in that the data to be transmitted and received is not stored in a pair of FIFO buffers. Rather, this data is stored in a RAM memory together with commands to be executed.
More particularly, the RAM memory is used to store data in transit between interfaces and peripherals, as well as control commands used to specify the length and destination of data together with other parameters associated with each transfer. The control circuit has chip select pins CS[0-n] for selecting a peripheral to communicate with when the interface is in a master device. The pins CS are not used when the interface is in a slave device. The information necessary for determining the desired chip select value on the relative pin is provided to the control circuit by the RAM memory.
The RAM memory is organized in three memory sections RECEIVE RAM, TRANSMIT RAM and COMMAND RAM, which are respectively for received data, data to be transmitted, and commands for configuring the interface in the desired mode. The pointer provided to the block CURRENT POINTER is used for pointing, at the same time, to a certain word in the memory section RECEIVE RAM, a certain word in the memory section TRANSMIT RAM, and a byte in the memory section COMMAND RAM identified by the address specified on the bus ADDR. The configuration commands to be executed are provided to the interface by an external controller each time that data passes through the interface.
This architecture is more advantageous than illustrated in FIG. 1 in that each time data to be transmitted and a configuration command have been written in the RAM memory, the interface may execute the programmed transfers simply by incrementing the pointer generated by the CURRENT POINTER without the intervention of an external controller. Moreover, when the data to be transmitted has been written in the memory, it may be retransmitted again many times to different peripherals without any further write operations in the memory simply by changing the bits of the configuration command that identify the different destinations.
However, QSPI interfaces require an external controller to write a command in the memory section COMMAND of the RAM memory each time data is exchanged, transmitted to, or received from a peripheral. This is disadvantageous because of the resulting burden placed on the external controller, making its architecture more complex.